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this is information on a product in full production. july 2014 docid025979 rev1 1/11 HSP051-4N10 4-line esd protection for high speed lines datasheet ? production data figure 1. functional schematic (top view) features ? flow-through routing to keep signal integrity ? ultralarge bandwidth: 10 ghz ? ultralow capacitance: ? 0.2 pf (i/o to i/o) ? 0.35 pf (i/o to gnd) ? very low dynamic resistance: 0.48 ? ? 100 ? differential impedance ? low leakage current: 100 na at 25 c ? extended operating junction temperature range: -40 c to 150 c ? rohs compliant benefits ? high esd protection level ? high integration ? suitable for high density boards complies with following standards ? mil-std 883g method 3015-7 class 3b: ?8 kv ? iec 61000-4-2 level 4: ? 8 kv (contact discharge) ? 15 kv (air discharge) applications the HSP051-4N10 is designed to protect against electrostatic discharge on sub micron technology circuits driving: ? hdmi 1.4 and 2.0 ? digital video interface ? display port ? usb 3.0 and 3.1 ? serial ata description the HSP051-4N10 is a 4-channel esd array with a rail to rail architecture designed specifically for the protection of high speed differential lines. the ultralow variation of the capacitance ensures very low influence on signal-skew. the large bandwidth make it compatible with hdmi 2.0 4k/2k (=5.94 gbps) and usb 3.1 (=10 gbps) the device is packaged in qfn 1.9 mm x 1 mm with a 400 m pitch. qfn 1.9x1 10l HSP051-4N10 i/o 1 i/o 2 gnd i/o 3 i/o 4 internally not connected gnd internally not connected 1 2 4 5 6 8 9 10 3 7 www.st.com
characteristics HSP051-4N10 2/11 docid025979 rev1 1 characteristics table 1. absolute maximum ratings t amb = 25 c symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 8 25 kv t j operating junction temperature range -40 to +150 c t stg storage temperature range -65 to +150 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics t amb = 25 c symbol test conditions min. typ. max. unit v br i r = 1 ma 4.5 5.8 v i rm v rm = 3.6 v 10 100 na v cl i pp = 1 a, 8/20 s 10 v v cl iec 61000-4-2, +8 kv contact (i pp = 16 a), measured at 30 ns 13 v rd dynamic resistance, pulse duration 100 ns i/o to gnd 0.48 ? gnd to i/o 0.96 c i/o - i/o v i/o = 0 v, f = 200 mhz to 9 ghz 0.2 0.3 pf c i/o - gnd v i/o = 0 v f = 200 mhz to 2.5 ghz 0.4 0.55 pf f = 2.5 ghz to 9 ghz 0.35 0.45 pf f c -3db 10 ghz z diff time domain reflectometry: t r = 200 ps (10 - 90%), z 0 = 100 ? 85 100 115 ? figure 2. leakage current versus junction temperature (typical values) figure 3. s21 attenuation measurement ir (na) 1 10 100 25 50 75 100 125 150 t j (c) v r = v rm = 3.6v s21 (db) 100k 1m 10m 100m 1g 10g -3 -2.5 -2 -1.5 -1 -0.5 0 0 v 2.5 v 3.6 v f (hz)
docid025979 rev1 3/11 HSP051-4N10 characteristics figure 4. eye diagram - hdmi mask at 3.4 gbps per channel (without HSP051-4N10) (1) figure 5. eye diagram - hdmi mask at 3.4 gbps per channel (1) (with HSP051-4N10) 1. hdmi specification conditions. this inform ation can be provided for other applications . please contact your local st office. figure 6. eye diagram - hdmi 2.0 mask at 5.94 gbps per channel (without HSP051-4N10) figure 7. eye diagram - hdmi 2.0 mask at 5.94 gbps per channel (with HSP051-4N10 figure 8. eye diagram - usb 3.0 mask at 5.0 gbps per channel (without HSP051-4N10) figure 9. eye diagram - usb 3.0 mask at 5.0 gbps per channel (with HSP051-4N10)
characteristics HSP051-4N10 4/11 docid025979 rev1 figure 10. eye diagram - usb 3.1 mask at 10.0 gbps per channel (without HSP051-4N10) figure 11. eye diagram - usb 3.1 mask at 10.0 gbps per channel (with HSP051-4N10) figure 12. esd response to iec 61000-4-2 (+8 kv contact discharge) figure 13. esd response to iec 61000-4-2 (-8 kv contact discharge) 50 v / div 20 ns / div v : peak clamping voltage cl v :clamping voltage at 30 ns cl v :clamping voltage at 60 ns cl v :clamping voltage at 100 ns cl 1 2 3 4 10 v 4 11 v 3 13 v 2 184 v 1 50 v / div -147 v 1 -13 v 2 -5 v 3 -2 v 4 v : peak clamping voltage cl v :clamping voltage @ 30 ns cl v :clamping voltage @ 60 ns cl v :clamping voltage @ 100 ns cl 1 2 3 4 20 ns / div figure 14. tlp measurement (pulse duration 100 ns) figure 15. tdr measurement 0 5 10 15 20 0 2 4 6 8 10121416182022 ipp (a) vcl (v) io/gnd gnd/io
docid025979 rev1 5/11 HSP051-4N10 package information 2 package information ? epoxy meets ul94, v0 ? lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 16. qfn 1.9x1 10l dimension definitions d e a b e e2 d2 k l2 a1 top view side view bottom view
package information HSP051-4N10 6/11 docid025979 rev1 table 3. qfn 1.9x1 10l dimension values ref. dimensions millimeters min. typ. max. a 0.29 0.32 0.35 a1 0.00 0.02 0.05 b 0.15 0.20 0.25 d 1.85 1.90 1.95 d2 0.15 0.20 0.25 e 0.95 1.00 1.05 e2 0.88 0.93 0.98 e0.40 k0.21 l2 0.02 0.05 0.07 figure 17. footprint recommendations (dimensions in mm) figure 18. marking 0,2 0,4 0,56 0,93 0,2 0,21 0,4 hc
docid025979 rev1 7/11 HSP051-4N10 package information figure 19. qfn 1.9x1 10l tape and reel specification
recommendation on pcb assembly HSP051-4N10 8/11 docid025979 rev1 3 recommendation on pcb assembly figure 20. recommended stencil window position 3.1 solder paste 1. use halide-free flux, qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste recommended. 3. offers a high tack force to resist component displacement during pcb movement. 4. use solder paste with fine particles: powder particle size 20-45 m. 3.2 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 0,19 0,53 0,66 0,14 0,24 0,4 0,4
docid025979 rev1 9/11 HSP051-4N10 recommendation on pcb assembly 3.3 pcb design 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks and open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. figure 21. printed circuit board layout recommendations 3.4 reflow profile figure 22. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. maximum soldering profile corresponds to the latest ipc/jedec j-std-020. 9ldwr *1' 9ldwr *1' ?p )rrwsulqw sdg 3&%wudfnv 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
ordering information HSP051-4N10 10/11 docid025979 rev1 4 ordering information figure 23. ordering information scheme 5 revision history table 4. ordering information order code marking package weight base qty delivery mode HSP051-4N10 hc qfn-10l 1.61 mg 7000 tape and reel hsp 05 1 - 4 n10 high speed line protection breakdown voltage version number of lines package qfn-10l 1.9x1.0mm table 5. document revision history date revision changes 11-jul-2014 1 initial release.
docid025979 rev1 11/11 HSP051-4N10 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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